Through Glass Vias (TGVs)
Through Glass Vias (TGVs) provide vertical electrical interconnects through glass substrates, enabling compact and high-density routing for 2.5D and 3D semiconductor packaging. They support improved signal integrity, reduced parasitics, and reliable power delivery in advanced packaging designs such as chiplets, RF modules, and high-performance computing.
Through Glass Via Fabrication with Chemical Etching
3DGS uses a non-mechanical chemical etching process for through glass via fabrication, helping maintain the structural integrity of the glass while enabling consistent via quality at scale. Compared to mechanical drilling methods, chemical etching reduces the risk of micro-cracking and edge damage, which can impact long-term reliability in high-density packaging designs.
Built on our APEX® Glass platform, this batch-based process supports tight dimensional control and repeatable via geometry, making it well-suited for TGVs in advanced packaging applications such as glass interposers, RF module integration, photonics packaging, and chiplet-based architectures.
Improved Performance with Through Glass Vias (TGVs)
Traditional packaging materials such as organic laminates, alumina, and silicon often limit performance in high-frequency and high-density designs due to higher dielectric loss, surface roughness, and routing constraints. Through Glass Vias (TGVs) help overcome these limitations by enabling vertical interconnects in glass substrates with improved electrical isolation and reduced parasitics.
By supporting shorter interconnect paths and more stable substrate behavior, TGV-based glass platforms can improve signal integrity, enable finer routing density, and deliver more consistent performance in RF, mmWave, HPC and advanced semiconductor packaging applications.
APEX® Glass Platform: High-Aspect-Ratio Via Capabilities
APEX® Glass supports dense via arrays with flexible geometries for high-aspect-ratio structures, enabling heterogeneous integration projects where RF, logic, and photonic components need to coexist on a single substrate. This capability gives design teams routing flexibility between substrate layers and supports various component integration strategies, including TGV-based vertical interconnect designs.
• Via diameters from 30 µm to 300 µm with multiple sizes on a single substrate
• Aspect ratios up to 8:1 for through-hole configurations
• Anisotropic sidewall profiles exceeding 88 degrees for vertical interconnects
• Edge-to-edge via spacing down to 10 µm for high-density routing
• Tight dimensional tolerances maintained across production runs
Integration with Other Components
3DGS provides end-to-end glass integration services that go beyond via formation. We support complete advanced packaging flows, including through-hole creation, copper-filled via processing, redistribution layer (RDL) metallization, and solder dam integration—helping customers move from prototype designs to qualification-ready hardware.
Copper-filled through-glass vias enable robust vertical interconnects with improved conductivity and stable electrical performance for high-density packaging applications.
Copper-filled via capabilities include:
High-conductivity copper fill for low electrical resistance
Fully metal-filled structures engineered to minimize voiding
Aspect ratio support up to 8:1 for filled via configurations
We collaborate closely with customers to support prototyping, pilot builds, and scalable low-to-high volume manufacturing based on program requirements.